1. Field of the Invention
This invention is concerned with data communication and is more particularly concerned with processing incoming packets of data
2. Background of the Invention
A considerable number of data communication protocols have been developed. One protocol which is widely used, for dedicated storage networks and other applications, is the Fibre Channel protocol (e.g., ANSI X3T11 Fibre Channel Standards).
FIG. 1 is a block diagram illustration of a data communication controller arrangement that is suitable for use with the Fibre Channel protocol.
In FIG. 1, a network physical interface block 10 receives an incoming stream of data from a network (not shown). A port logic block 12 is coupled to the physical interface block 10. The inbound data communication stream is passed from the port logic block 12 to an inbound interface block 14, which includes a FIFO (first-in-first-out) pre-buffer 16. The inbound data communication stream proceeds from the inbound interface block 14 to an inbound processing block 18. The inbound processing block 18 includes processing and control logic circuitry 20 and an inbound frame buffer 22. The inbound data that has been buffered in the inbound frame buffer 22 is provided to one or more DMA (direct memory access) engines 24. The DMA engines 24 are in two-way communication with a host system bus (not shown) via a host system bus interface 26.
In the outbound data path, outbound data is provided from the DMA engines 24 to an outbound processing block 28. The outbound processing block 28 includes processing and control logic circuitry 30 and an outbound frame buffer 32.
The outbound data stream continues from the outbound frame buffer 32 to outbound interface block 34, which includes a FIFO post-buffer 36. The outbound data stream continues from the outbound interface block 34 through the port logic 12 and the network physical interface 10 to the data network itself.
Details of processing performed with respect to the inbound data path of a Fibre Channel controller will now be described with reference to FIG. 2. In FIG. 2, block 38, which corresponds to the inbound side of the network physical interface 10 (FIG. 1), represents the “physical layer” (FC-0) of the Fibre Channel protocol. Block 38 performs serial-to-parallel conversion and synchronizes and maintains byte timing.
Block 40 represents the FC1 and FC-AL (arbitrated loop) layers of the Fibre Channel protocol and corresponds to the inbound side of port logic block 12 (FIG. 1). Block 40 performs 10 bit to 8 bit code conversion, compensation for clock timing differences, ordered set decode and loop management. Block 40 also detects errors such as loss of word or byte synchronization, 8b 10b code violation and running disparity error, and recognizes a link reset command.
Block 42 corresponds to frame processing logic that is included in inbound interface block 14 (FIG. 1). Block 42 manages the FIFO prebuffer 16 (FIG. 1) and routes frames to the correct frame buffer depending on frame type. Block 42 also performs error detection functions such as CRC (cyclic redundancy check), maximum frame length, correctness of the destination node ID, detection of a valid end of frame (EOF) sequence and detection of whether the frame is in an unsupported class, i.e., is of a quality of service class that is not supported by the receiving facility.
As shown in FIG. 2, the inbound data path proceeds through blocks 38, 40 and 42 to frame buffers 22. A microprocessor 44 is in communication with the frame buffers 22 and performs software processing on incoming data frames. Microprocessor 44 corresponds to at least part of the processing and control logic circuitry 20 shown in FIG. 1. (The microprocessor 44 may also perform at least some of the functions of the outbound processing and control logic circuitry 30 shown in FIG. 1.)
Microprocessor 44 may be a single processor or multiple processors.
The processing performed by the microprocessor 44 may include reading the headers of the inbound data frames, determining the types of the frames, relating the data frames to exchange context blocks, and managing the frame buffers 22. The microprocessor 44 may also handle communication with a host processor, perform higher level error checking in addition to the error checks performed by blocks 38, 40, 42 and generally control operation of a controller card on which the inbound and outbound control functions are performed.
The following table indicates the format of data frames used in the Fibre Channel protocol.
TABLE 1Frame FormatComponentNo. of BytesSOF 4Header24Data0-2112CRC 4EOF 4
In Table 1 “SOF” refers to the start of frame sequence, “CRC” refers to cyclic redundancy check data and “EOF” refers to the end of frame sequence.
The format of the header data in the frames of the Fibre Channel protocol is indicated by the following table.
TABLE 2Header FormatFieldNo. of BytesR—CTL (Routing Control)1D—ID (Destination ID)3[reserved]1S—ID (Source ID)3TYPE (Data Type)1F—CTL (Frame Control)3SEQ—ID (Sequence ID)1DF—CTL (Data Field Control)1SEQ—CNT (Sequence Count)2OX—ID (Originator Exchange ID)2RX—ID (Responder Exchange ID)2Parameter4
The header consists of 6 words of 4 bytes each. The “Routing Control” field (first word, first byte) is used with the Type field (discussed below) to identify the function of the frame.
The “Destination ID” field (first word, last three bytes) represents the address of the destination node. The “Source ID” field (second word, last three bytes) represents the address of the source node. The “Data Type” field (third word, first byte) represents the protocol type for the data frames.
The “Frame Control” field (third word, last three bytes) provides indications as to whether the sender is the originator or responder of the exchange, whether it is the first or last sequence, whether sequence initiative is passed, whether the relative offset is in the Parameter field, and how many field bytes there are. This information is primarily used by the microprocessor 44 when processing frames and setting up direct memory access operations in main memory.
The “Sequence ID” field (fourth word, first byte) is a number that uniquely identifies an open sequence for a destination and source node pair.
The “Data Field Control” field (fourth word, second byte) indicates the presence of additional optional headers at the beginning of the data field.
The “Sequence Count” field (fourth word, last two bytes) identifies the ordering of frames within a sequence starting with “000” and incrementing by “1” for each frame sent.
The “Originator Exchange ID” field (fifth word, first two bytes) is a unique ID number assigned by the originator of an exchange.
The “Responder Exchange ID” field (fifth word, last two bytes) is a unique ID number assigned by the responder of an exchange.
The “parameter” field (sixth word) performs various functions depending on the type of the frame, and the type of device involved in the exchange.
In an arrangement of the type illustrated in FIGS. 1 and 2, the present inventors have recognized that it would be desirable to reduce the processing load on the microprocessor 44 (FIG. 2). With reduction in the processing load it may be possible to obtain an improvement in performance, yielding faster processing and a higher frame rate. Also more processor cycles may be available for other tasks. Alternatively, or in addition, the processor clock rate may be reduced, allowing for use of a cheaper, simpler processor having less cache and consuming less power.